View MT8VDDT1664AG-202A1_7896855.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance note : symbols in parentheses are not used on this module but may be used for other modules in this product family. they are for reference only. pin assignment ddr sdram dimm module mt8vddt1664a, mt16vddt3264a for the latest data sheet, please refer to the micron web site: www.micron.com/mti/msp/html/datasheet.html features ? 184-pin dual in-line memory modules (dimm) utilizes 100 mhz and 133 mhz ddr sdram components ecc-optimized pinout 128mb (16 meg x 64), 256mb (32 meg x 64) v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v 2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle bidirectional data strobe (dqs) transmitted/ received with data, i.e., source-synchronous data capture differential clock inputs (ck0 and ck0#) four internal banks for concurrent operation programmable burst lengths: 2, 4 or 8 auto precharge option auto refresh and self refresh modes 15.6s maximum average periodic refresh interval options marking package 184-pin dimm (gold) g frequency/cas latency 266 mhz/cl = 2 (133 mhz ddr sdrams) -262 266 mhz/cl = 2.5 (133 mhz ddr sdrams) -265 200 mhz/cl = 2 (100 mhz ddr sdrams) -202 pin symbol pin symbol pin symbol pin symbol 1v ref 47 dqs8 93 v ss 139 v ss 2 dq0 48 a0 94 dq4 140 dqs17 3v ss 49 cb2 95 dq5 141 a10 4 dq1 50 v ss 96 v dd q 142 cb6 5 dqs0 51 cb3 97 dqs9 143 v dd q 6 dq2 52 ba1 98 dq6 144 cb7 7v dd 53 dq32 99 dq7 145 v ss 8 dq3 54 v dd q 100 v ss 146 dq36 9nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 v dd 11 v ss 57 dq34 103 nc ( a13 ) 149 dqs13 12 dq8 58 v ss 104 v dd q 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 v ss 15 v dd q 61 dq40 107 dqs10 153 dq44 16 ck1 62 v dd q 108 v dd 154 ras# 17 ck1# 63 we# 109 dq14 155 dq45 18 v ss 64 dq41 110 dq15 156 v dd q 19 dq10 65 cas# 111 cke1 157 s0# 20 dq11 66 v ss 112 v dd q 158 s1# 21 cke0 67 dqs5 113 nc ( ba2 ) 159 dqs14 22 v dd q 68 dq42 114 dq20 160 v ss 23 dq16 69 dq43 115 nc ( a12 ) 161 dq46 24 dq17 70 v dd 116 v ss 162 dq47 25 dqs2 71 nc (s2#) 117 dq21 163 nc (s3#) 26 v ss 72 dq48 118 a11 164 v dd q 27 a9 73 dq49 119 dqs11 165 dq52 28 dq18 74 v ss 120 v dd 166 dq53 29 a7 75 ck2# 121 dq22 167 nc (feten) 30 v dd q 76 ck2 122 a8 168 v dd 31 dq19 77 v dd q 123 dq23 169 dqs15 32 a5 78 dqs6 124 v ss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 v ss 80 dq51 126 dq28 172 v dd q 35 dq25 81 v ss 127 dq29 173 nc 36 dqs3 82 v ddid 128 v dd q 174 dq60 37 a4 83 dq56 129 dqs12 175 dq61 38 v dd 84 dq57 130 a3 176 v ss 39 dq26 85 v dd 131 dq30 177 dqs16 40 dq27 86 dqs7 132 v ss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 v ss 88 dq59 134 cb4 180 v dd q 43 a1 89 v ss 135 cb5 181 sa0 44 cb0 90 wp 136 v dd q 182 sa1 45 cb1 91 sda 137 ck0 183 sa2 46 v dd 92 scl 138 ck0# 184 v ddspd 184-pin dimm (front view)
2 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance part numbers part number configuration system bus speed mt8vddt1664ag-262__ 16 meg x 64 cl = 2, 266 mhz mt8vddt1664ag-265__ 16 meg x 64 cl = 2.5, 266 mhz mt8vddt1664ag-202__ 16 meg x 64 cl = 2, 200 mhz mt16vddt3264ag-262__ 32 meg x 64 cl = 2, 266 mhz mt16vddt3264ag-265__ 32 meg x 64 cl = 2.5, 266 mhz mt16vddt3264ag-202__ 32 meg x 64 cl = 2, 200 mhz note : all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt16vddt3264ag-262 a1 general description the mt8vddt1664a and mt16vddt3264a are high-speed cmos, dynamic random-access, 64mb and 128mb memories organized in a x64 configuration. these modules use internally configured quad-bank ddr sdrams. these ddr sdram modules use a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram module effectively consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two correspond- ing n -bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. these ddr sdram modules operate from a differ- ential clock (ck0 and ck0#); the crossing of ck0 going high and ck0# going low will be referred to as the positive edge of ck0. commands (address and control signals) are registered at every positive edge of ck0. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck0. read and write accesses to the ddr sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. these ddr sdram modules provide for program- mable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdr sdram modules, the pipelined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effec- tive bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are com- patible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. for more information regarding ddr sdram operation, refer to the 128mb x4, x8, x16 ddr sdram data sheet. serial presence-detect operation the ddr sdram modules incorporate serial pres- ence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing param- eters. the remaining 128 bytes of storage are available for use by the customer. system read/write opera- tions between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses. key ddr sdram component timing parameters module speed clock frequency (1/ t ck) marking grade cl = 2* cl = 2.5* -262/-265 -7 133 mhz 143 mhz -202 -75 100 mhz 133 mhz *cl = cas (read) latency
3 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance functional block diagram mt8vddt1664a (128mb) note: all resistor values are 22 ohms unless otherwise specified. u1,3,6,8,11,13,14,16 = mt46v16m8tg ddr sdrams a0 sa0 serial pd u20 sda a1 sa1 a2 sa2 ba0, ba1 a0-a11 ras# ba0, ba1: sdrams u1,3,6,8,11,13,14,16 a0-a11: sdrams u1,3,6,8,11,13,14,16 ras#: sdrams u1,3,6,8,11,13,14,16 cas#: sdrams u1,3,6,8,11,13,14,16 cke0: sdrams u1,3,6,8,11,13,14,16 we#: sdrams u1,3,6,8,11,13,14,16 cas# cke0 we# v ref v ss sdrams u1,3,6,8,11,13,14,16 sdrams u1,3,6,8,11,13,14,16 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u14 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u13 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs9 rs0# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 wp scl dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs13 dqs4 dqs10 dqs1 dqs14 dqs5 dqs11 dqs2 dqs15 dqs6 dm cs# dqs u16 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dm cs# dqs dm cs# dqs dqs12 dqs3 dqs16 dqs7 v ddq v dd sdrams u1,3,6,8,11,13,14,16 sdrams u1,3,6,8,11,13,14,16 sdram x 2 ck0 ck0# 120 sdram x 3 ck1 ck1# 120 sdram x 3 ck2 ck2# 120 47k
4 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance functional block diagram mt16vddt3264a (256mb) note: all resistor values are 22 ohms unless otherwise specified. u1-u8, u10-u17 = mt46v16m8tg ddr sdrams a0 sa0 serial pd u20 sda a1 sa1 a2 sa2 ba0, ba1 a0-a11 ras# ba0, ba1: sdrams u1-u8, u10-u17 a0-a11: sdrams u1-u8, u10-u17 ras#: sdrams u1-u8, u10-u17 cas#: sdrams u1-u8, u10-u17 cke0: sdrams u1-u8 cke1: sdrams u10-u17 we#: sdrams u1-u8, u10-u17 cas# cke0 cke1 we# v ref v ss sdrams u1-u8, u10-u17 sdrams u1-u8, u10-u17 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs9 rs0# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 wp scl u10 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u12 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u14 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 rs1# dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs13 dqs4 dqs10 dqs1 dqs14 dqs5 u15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dqs11 dqs2 dqs15 dqs6 dm cs# dqs dm cs# dqs u7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u16 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs12 dqs3 dqs16 dqs7 u13 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs u17 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs v ddq v dd sdrams u1-u8, u10-u17 sdrams u1-u8, u10-u17 sdram x 4 ck0 ck0# 120 sdram x 6 ck1 ck1# 120 sdram x 6 ck2 ck2# 120 47k
5 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance pin descriptions pin numbers symbol type description 63, 65, 154 we#, cas#, input command inputs: we#, cas# and ras# (along with ras# s0#, s1#) define the command being entered. 137, 138, 16, 17, 76, 75 ck0, ck0#, input clocks: ck and ck# are differential clock inputs. all ck1, ck1#, address and control input signals are sampled on the ck2, ck2# crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs) is referenced to the crossings of ck and ck#. 21, 111 cke0, cke1 input clock enables: cke0 and cke1 activate (high) and deactivate (low) internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke0 and cke1 are synchronous for all functions except for disabling outputs, which is achieved asynchronously. cke0 and cke1 must be maintained high throughout read and write accesses. input buffers (excluding ck0, ck0# and cke) are disabled during power-down. input buffers (excluding cke0 and cke1) are disabled during self refresh. cke0 and cke1 are sstl_2 inputs but will detect an lvcmos low level after v dd is applied. 157, 158 s0#, s1# input chip selects: s0# and s1# ena ble (registered low) and disable (registered high) the command decoder. all com- mands are masked when s0# and s1# are registered high. s0# and s1# provide for external bank selection on systems with multiple banks. s0# and s1# are considered part of the command code. 59, 52 ba0, ba1 input bank addresses: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. 48, 43, 41, 130, 37, 32, a0-a11 input address inputs: a0-a11 are sampled during the active 125, 29, 122, 27, 141, command (row-address a0-a11) and read/write 118 command (column-address a0-a9, with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). the address inputs also provide the op-code during a mode register set command. 1v ref input sstl_2 reference voltage. 82 v ddid input v dd identification flag. 90 wp input write protect: serial presence-detect hardware write protect. 92 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module.
6 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance pin descriptions pin numbers symbol type description 181, 182, 183 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 44, 45, 49, 51, 134, 135, cb0-cb7 input/ data i/os: check bits. 142, 144 output 5, 14, 25, 36, 56, 67, 78, dqs0-dqs17 input/ data strobes: output with read data, input with write data. 86, 47, 97, 107, 119, output edge-aligned with read data, centered in write data. used 129, 149, 159, 169, 177, to capture write data. 140 2, 4, 6, 8, 12, 13, 19, 20, dq0-dq63 input/ data i/os: data bus. 23, 24, 28, 31, 33, 35, 39, output 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 91 sda input/ serial presence-detect data: sda is a bidirectional pin output used to transfer addresses and data into and out of the presence-detect portion of the module. 15, 22, 30, 54, 62, 77, 96, v dd q supply dq power supply: +2.5v +0.2v. 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, v dd supply power supply: +2.5v +0.2v. 120, 148, 168 3, 11, 18, 26, 34, 42, 50, v ss supply ground. 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 v ddspd supply serial eeprom positive power supply: 2.2v to 3.7v. this supply is isolated from the v dd /v dd q supply. 9, 10, 71, 101, 102, 103, nc ? no connects. 113, 115, 163, 167, 173
7 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance scl sda data stable data stable data change figure 1 data validity scl sda start bit stop bit figure 2 definition of start and stop scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an ac- knowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each subsequent eight- bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
8 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance serial presence-detect matrix byte description entry (version) mt8vddt1664a mt16vddt3264a 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type sdram ddr 07 07 3 number of row addresses 12 0c 0c 4 number of column addresses 10 0a 0a 5 number of banks 1 or 2 01 02 6 module data width 64 40 40 7 module data width (continued) 0 00 00 8 module voltage interface levels sstl 2.5v 04 04 9 sdram cycle time, t ck 7 (-262) 70 70 (cas latency = 2.5) 7.5 (-265) 75 75 8 (-202) 80 80 10 sdram access from clock, t ac 0.75 (-262/-265) 75 75 (cas latency = 2.5) 0.8 (-202) 80 80 11 module configuration type non-ecc 00 00 12 refresh rate/type 15.6s/self 80 80 13 sdram width (primary sdram) 8 08 08 14 error-checking sdram data width none 00 00 15 minimum clock delay, back-to-back 1 01 01 random column access 16 burst lengths supported 2, 4, 8 0e 0e 17 number of banks on sdram device 4 04 04 18 cas latencies supported 2, 2.5 0c 0c 19 cs latency 1 02 02 20 we latency 1 02 02 21 sdram module attributes 20 20 22 sdram device attributes: general 00 00 23 sdram cycle time, t ck 7.5 (-262) 75 75 (cas latency = 2) 10 (-265/-202) a0 a0 24 sdram cycle time, t ck 7 (-262) 70 70 (cas latency = 2) 7.5 (-265) 75 75 8 (-202) 80 80 25 sdram cycle time, t ck ? 00 00 (cas latency = 1) 26 sdram access from clk , t ac ? 00 00 (cas latency = 1) 27 minimum row precharge time, t rp 20 50 50 28 minimum row active to row active, 15 3c 3c t rrd 29 minimum ras# to cas# delay, t rcd 20 50 50 30 minimum ras# pulse width, t ras 45 (-262/-265) 2d 2d 50 (-202) 32 32 31 module bank density 128mb 20 20 note: ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ?
9 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance serial presence-detect matrix (continued) byte description entry (version) mt8vddt864a mt16vddt1664a 32 address and command setup time, t is 0.75 (-262/-265) 75 75 1.2 (-202) c0 c0 33 address and command hold time, t ih 0.75 (-262/-265) 75 75 1.2 (-202) c0 c0 34 data/data mask input setup time, t ds 0.5 (-262/-265) 50 50 0.6 (-202) 60 60 35 data/data mask input hold time, t dh 0.5 (-262/-265) 50 50 0.6 (-202) 60 60 36-61 reserved 00 00 62 spd revision 0 00 00 63 checksum for bytes 0-62 -262 34 35 -265 69 6a -202 45 46 64 manufacturer ? s jedec id code micron 2c 2c 65-71 manufacturer ? s jedec id code ff ff (continued) 72 manufacturing location 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 73-90 module part number (ascii) xx 91 pcb identification code 1 01 01 202 02 303 03 404 04 505 05 606 06 707 07 808 08 909 09 92 identification code (continued) 0 00 00 93 year of manufacture in bcd xx 94 week of manufacture in bcd xx 95-98 module serial number xx 99-127 manufacturer-specific data (rsvd) ?? note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data.
10 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance note: 1. cke is high for all commands shown except self refresh. 2. ba0-ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combinations of ba0-ba1 are reserved). a0-a11 provide the op- code to be written to the selected mode register. 3. ba0-ba1 provide bank address and a0-a11 provide row address. 4. ba0-ba1 provide bank address; a0-a9 provide column address; a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 5. a10 low: ba0-ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0-ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 9. deselect and nop are functionally interchangeable. 10. used to mask write data; provided coincident with the corresponding data. truth table 1 ? commands (note: 1) name (function) cs# ras# cas# we# addr notes deselect (nop) h x x x x 9 no operation (nop) l h h h x 9 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 burst terminate l h h l x 8 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh l l l h x 6, 7 (enter self refresh mode) load mode register l l l l op-code 2 truth table 1a ? dm operation name (function) dm dqs notes write enable l valid 10 write inhibit hx 10 commands truth table 1 provides a general reference of avail- able commands. for a more detailed description of commands and operations, refer to the 128mb: x4, x8, x16 sdram ddr data sheet.
11 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a11 ba1 ba0 10 11 12 13 * m13 and m12 (ba0 and ba1) must be ? 0, 0 ? to select the base mode register (vs. the extended mode register). m9 m10 m11 table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 00-1 0-1 11-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 note: 1. for a burst length of two, a1-a9 select the two- data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-a9 select the four- data-element block; a0-a1 select the first access within the block. 3. for a burst length of eight, a3-a9 select the eight-data-element block; a0-a2 select the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. figure 4 mode register definition
12 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance dc electrical characteristics and operating conditions (notes: 1-6) (0 c t a +70 c; v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v) parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q 2.3 2.7 v i/o reference voltage v ref 0.49 x v dd q 0.51 x v dd qv 7 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 8 input high (logic 1) voltage v ih v ref + 0.18 v dd + 0.3 v 9 input low (logic 0) voltage v il -0.3 v ref - 0.18 v 9 clock input voltage level; ck0 and ck0# v in -0.3 v dd q + 0.3 v clock input differential voltage; ck0 and ck0# v id 0.36 v dd q + 0.6 v 10 clock input crossing point voltage; ck0 and ck0# v ix 1.15 1.35 v 11 input leakage current we#, ras#, cas#, ba0 i i 1 -32 32 a 12 any input 0v v in v dd ba1 (all other pins not under test = 0v) s0#, s1#, cke0, cke1 i i 2 -16 16 a ck, ck# i i 3 -12 12 a 12 output leakage current dq0-dq63, i oz -10 10 a 12 (dqs are disabled; 0v v out v dd q) dqs0-dqs17 output levels output high current (v out = 1.95v, maximum v tt )i oh -15.2 ? ma output low current (v out = 0.35v, minimum v tt )i ol 15.2 ? ma absolute maximum ratings* voltage on v dd supply relative to v ss ..................................... -1v to +4.6v voltage on v dd q supply relative to v ss ..................................... -1v to +3.6v voltage on v ref and inputs relative to v ss ..................................... -1v to +3.6v voltage on i/o pins relative to v ss ........................ -0.5v to v dd q +0.5v operating temperature, t a (ambient) ... 0c to +70c storage temperature (plastic) ............ -55c to +150c power dissipation ................................................. 18w short circuit output current ............................. 50ma *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: output (v out ) timing reference point 25 ? 25 ? v tt 30pf
13 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance notes: (continued) 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd q is recognized as low. 7. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak- to-peak noise on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, v ref is allowed 25mv for dc error and 25mv for ac noise. 8. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 9. the dc values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. the inputs require the ac value to be achieved during signal transition edge. 10. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 11. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 12. 64mb module values will be half of those shown.
14 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance ac operating conditions (notes: 1-7) (0 c t a +70 c; v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v) parameter/condition symbol min max units notes input high (logic 1) voltage; dq, dqs and dm signals v ih ( ac )v ref + 0.35 ? v 6, 8 input low (logic 0) voltage; dq, dqs and dm signals v il ( ac ) ? v ref - 0.35 v 6, 8 clock input differential voltage; ck and ck# v id ( ac ) 0.7 v dd q + 0.6 v 9 clock input crossing point voltage; ck and ck# v ix ( ac ) 0.5 x v dd q - 0.2 0.5 x v dd q + 0.2 v 10 note: 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. input slew rate = 1v/ns. if the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. if the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the v il ( ac ) maximum and v ih ( ac ) minimum points. for slew rates between 0.5v/ns and 1v/ns, t is and t ih must be increased by at least 20 percent. 7. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd q is recognized as low. 8. the dc values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. the inputs require the ac value to be achieved during signal transition edge. 9. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 10. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. output (v out ) timing reference point 25 ? 25 ? v tt 30pf
15 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance i dd specifications and conditions* (notes: 1-8; notes appear below and on next page) (0 c t a +70 c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v) parameter/condition symbol size -262 -265 -202 units notes operating current: one bank; active-precharge; t rc = i dd 0 64mb 1,040 1,000 960 ma 9 t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cyle; address and control inputs changing 128mb 1,560 1,480 1,440 once per clock cycle; cl = 2.5 operating current: one bank; active-read-precharge; i dd 1 64mb 840 800 800 ma 9 burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; i out = 0ma; address and control inputs changing once per clock cycle 128mb 1,360 1,280 1,280 precharge power-down standby current: all banks i dd 2p 64mb 280 240 240 ma idle; power-down mode; cke = low; t ck = t ck min 128mb 560 480 480 idle standby current: cs# = high; all banks idle; i dd 2n 64mb 480 440 400 ma cke = high; t ck = t ck min; address and other control inputs changing once per clock cycle 128mb 960 880 800 active power-down standby current: one bank i dd 3p 64mb 280 240 240 ma active; power-down mode; cke = low; t ck = t ck min 128mb 560 480 480 active standby current: cs# = high; cke = high; i dd 3n 64mb 520 480 480 ma 9 one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; 128mb 1,040 960 960 address and other control inputs changing once per clock cycle operating current: burst = 2; reads; continuous burst; i dd 4r 64mb 1,040 1,000 920 ma one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; i out = 0ma 128mb 1,560 1,480 1,400 operating current: burst = 2; writes; continuous burst; i dd 4w 64mb 920 840 800 ma one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; dq, dm and dqs inputs 128mb 1,440 1,320 1,280 changing twice per clock cycle auto refresh current t rc = t rfc min i dd 5 64mb 1,240 1,160 1,120 ma 9 128mb 2,480 2,320 2,240 t rc = 15.625s i dd 6 64mb 200 200 200 ma 10 128mb 400 400 400 self refresh current: cke 0.2v standard i dd 7 64mb 16 16 24 ma 11 128mb 32 32 48 low power (l) i dd 8 64mb 8 8 8 ma 11 128mb 16 16 16 max *specifications based on 64mb ddr sdram components. note: 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
16 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance notes: (continued) 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 7. i dd specifications are tested after the device is properly initialized. 8. input slew rate = 1v/ns. if the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. if the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the v il ( ac ) maximum and v ih ( ac ) minimum points. for slew rates between 0.5v/ns and 1v/ns, t is and t ih must be increased by at least 20 percent. 9. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras max for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras. 10. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 11. enables on-chip refresh and address counters. output (v out ) timing reference point 25 ? 25 ? v tt 30pf
17 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance sdram ddr component* ac electrical characteristics (notes: 1-9; notes appear below an don next page) (0 c t a + 70 c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v) ac characteristics -262 -265 -202 parameter symbol min max min max min max units notes access window of dqs from ck/ck# t ac -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock cycle time cl = 2.5 t ck 7 15 7.5 15 8 15 ns cl = 2 t ck 7.5 15 10 15 10 15 ns auto precharge write recovery plus precharge time t dal 35 35 35 ns dq and dm input hold time t dh 0.5 0.5 0.6 ns dq and dm input setup time t ds 0.5 0.5 0.6 ns dq and dm input pulse width (for each input) t dipw 1.75 1.75 2 ns access window of dqs from ck/ck# t dqsck -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq-dq skew (first to last transition per access) t dqsq 0.5 0.5 0.6 ns write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 t ck dq/dqs output valid window t dv 0.35 0.35 0.35 t ck 10 data-out high-impedance window from ck/ck# t hz -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 11 data-out low-impedance window from ck/ck# t lz -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 11 address and control input hold time t ih 0.75 0.75 1.1 ns 12 address and control input setup time t is 0.75 0.75 1.1 ns 12 address and control input pulse width t ipw 2 2 2.5 ns load mode register command cycle time t mrd 15 15 16 ns active to precharge command t ras 45 120,000 45 120,000 50 120,000 ns active to active/auto refresh command period t rc 65 65 70 ns auto refresh to active/ t rfc 75 75 80 ns auto refresh command period refresh to refresh command interval t refc 31.2 31.2 31.2 s 13 average periodic refresh interval t refi 15.6 15.6 15.6 s 13 active to read or write delay t rcd 20 20 20 ns precharge command period t rp 20 20 20 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 15 15 15 ns terminating voltage delay to v dd t vtd 0 0 0 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 0 ns 14, 15 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 16 dqs write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 1 1 1 t ck exit self refresh to non-read command t xsnr 75 75 80 ns exit self refresh to read command t xsrd 200 200 200 t ck *specifications for the ddr sdram components used on the module. note: 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
18 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance notes: (continued) 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. input slew rate = 1v/ns. if the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. if the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the v il ( ac ) maximum and v ih ( ac ) minimum points. for slew rates between 0.5v/ns and 1v/ns, t is and t ih must be increased by at least 20 percent. 7. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 8. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd q is recognized as low. 9. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 10. t dv is derived assuming a 45/55 clock high-to-low ratio. the t dv is improved directly proportional to the reduction in the clock high-to-low ratio. 11. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 12. input slew rate = 1v/ns. if the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. if the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the v il ( ac ) maximum and v ih ( ac ) minimum points. for slew rates between 0.5v/ns and 1v/ns, t is and t ih must be increased by at least 20 percent. 13. the refresh period 64ms. this equates to an average refresh rate of 15.625s. however, an auto refresh command must be asserted at least once every 31.2s; burst refreshing or postings greater than 2 are not allowed. 14. the minimum limit for this parameter is not a device limit. the device will operate with a negative value for this parameter, but system performance (bus turnaround) will degrade accordingly. 15. the specific requirement is that dqs be valid (high or low) on or before this ck edge. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dqss. 16. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. output (v out ) timing reference point 25 ? 25 ? v tt 30pf
19 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance capacitance (note: 1) parameter symbol min max min max units input/output capacitance: dqs, dqss, cbs c io 5.0 7.0 10.0 14.0 pf input capacitance: ck, ck# ci1 9 12 18 24 pf input capacitance: a0-a11, ba0/1, ras#, cas#, we# ci2 22 30 44 60 pf input capacitance: s0#, s1#, cke0, cke1 ci3 22 30 22 30 pf note: 1. this parameter is sampled. v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v, f = 100 mhz, t a = 25 c, v out ( dc ) = v dd q/2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 64mb 128mb
20 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance serial presence-detect eeprom dc operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ? 0.4 v input leakage current: v in = gnd to v dd i li ? 10 a output leakage current: v out = gnd to v dd i lo ? 10 a standby current: i sb ? 30 a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i cc ? 2ma scl clock frequency = 100 khz serial presence-detect eeprom ac operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 2 note: 1. all voltages referenced to v ss . note: 1. all voltages referenced to v ss . 2. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address.
21 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance spd eeprom scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0 s t hd:sta 4 s symbol min max units t high 4 s t low 4.7 s t r1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s
22 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance 184-pin dimm (128mb) 1.255 (31.88) 1.245 (31.62) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view back view .054 (1.37) .046 (1.17) 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) pin 184 pin 93 .150 (3.80) .150 (3.80) typ. .394 (10.00) typ. .157 (4.00) max note: all dimensions in inches (millimeters) max or typical where noted. min
23 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm41.p65 ? rev. 3/00 ?2000, micron technology, inc. 16, 32 meg x 64 ddr sdram dimms advance 184-pin dimm (256mb) 1.255 (31.88) 1.245 (31.62) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view back view .054 (1.37) .046 (1.17) 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) pin 184 pin 93 .150 (3.80) .150 (3.80) typ. .394 (10.00) typ. .157 (4.00) max 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc. note: all dimensions in inches (millimeters) max or typical where noted. min

▲Up To Search▲

Price & Availability of MT8VDDT1664AG-202A1

	To Download MT8VDDT1664AG-202A1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .